Due to the excellent material properties of GaN, transistors made of GaN are suitable for high voltage, high temperature and fast operation. One key application of GaN transistors is to make switching devices that can manage the electric power flow. For power switch applications, it is highly desirable to use transistors working in normally-off mode. In order to enable normally-off operation, it is imperative to have a gate dielectric which can allow a positive bias on the gate without having a trapping or leakage problem.
Gate dielectrics that are common in the prior art include silicon oxide (SiO2), silicon nitride (SiN), and aluminum oxide (Al2O3). While these dielectrics are good candidates for blocking leakage current, there are normally a high density of interface trap states between the III-Nitride semiconductors and the gate insulator. These trap states may cause an undesired threshold voltage shift. They may also provide an additional leakage path between the source and the drain.
The use of an AlN dielectric as a gate insulator is described by T. Hashizume, E. Alekseev, D. Pavlidis, K. Boutros, and J. Redwing, “Capacitance-Voltage Characterization of AlN/GaN Metal-Insulator-Semiconductor Structures Grown on Sapphire Substrate by Metalorganic Chemical Vapor Deposition,” Journal of Applied Physics, vol. 88, no. 4, pp. 1983-1986, August 2000, and T. Chen, G. Jiao, Z. Li, F. Li, K. Shao, and N. Yang, “AlGaN/GaN MIS HEMT with ALD Dielectric,” Digest of CS MANTECh Conference, pp. 227-230, April 2006.
The disadvantage of a gate insulator or dielectric formed of AlN as described by these references is that the forward gate leakage is still high, and is typically greater than 10 μA/mm at 3V of forward gate bias.
S. D. Burnham, K. Boutros, P. Hashimoto, C. Butler, D. W. S. Wong, M. Hu, and M. Micovic, “Gate-recessed Normally-off GaN-on-Si HEMT using a new O2/BCl3 Digital Etching Technique,” at ICNS-8 Jeju, Korea, 2009, and U.S. patent application Ser. No. 12/909,497, filed on Oct. 21, 2010, describe methods of performing a gate recess etch with precise depth control and good uniformity.
Having a gate dielectric with low interface trap density and low leakage is a long-felt need for GaN devices. Researchers have tried different dielectrics for gate insulators in III-Nitride semiconductors. As discussed above, in spite of many years of research, there is little success of having low interface trap density, indicated by threshold voltage hysteresis, maximum drain current density, and off-state drain leakage current, and low gate leakage current at the same time, especially for normally-off transistors.
What is needed is a gate insulator that forms a good interface with III-Nitride semiconductors and which has a low interface trap density and a very low leakage current. Also desirable is a threshold voltage greater than 3V, a threshold voltage hysteresis less than 0.3V, gate leakage current density less than 10 μA/mm, off-state drain leakage current density less than 10 μA/mm, and maximum drain current density greater than 150 mA/mm. The embodiments of the present disclosure answer these and other needs.